Tuesday, January 25, 2000

The features

The GA-71X is based around the IronGate (AMD750) chipset designed by AMD. The chipset is composed of two chips: The AMD751 Southbridge (PCI/AGP), and the AMD 756 (PCI/ISA/IDE) Northbridge. While larger than most conventional boards, the GA-71X does not posses a greatly extended feature set over those boards based around Intel chips. In effect, the GA-71X embraces a similar design stance to the Fester motherboard originally designed by AMD. The major difference between the AMD Fester, and the Gigabyte GA-71X is the 8 voltage regulators found behind the processor slot. While the original AMD design had radiators placed at each of those points, Gigabyte saw fit to ignore that detail. Otherwise, the GA-71X is quite the conventional motherboard.

With the Gigabyte GA-71X, the expansion possibilities are taken care of by its 5 PCI slots, 2 ISA slots, and single AGP port. Finally, 3 168-pin DIMM sockets permit the installation of a maximum of 768MB of memory.

Speaking of memory, note that it is futile to install anything other that PC100 memory on this board, as it is at that default and maximum 100Mhz FSB that the system bus is set on this board. Contrary to most boards, the Gigabyte GA-71X is deprived of either jumper, or BIOS options to adjust the frequency of the system bus, or the clock multiplier. Thus, with the GA-71X, we can only obtain a frequency of 100Mhz, and thus it is not possible to Overclock the board in this analysis.

On the other hand, one particularity that distinguishes the GA-71X is a series of options for adjusting the timing of the memory. Among those options are:

SDRAM PH Limit: Specify the number of consecutive page-hit requests to allow before choosing a
                              non-page-hit request .

SDRAM Idle Limit: Specify the number of idle cycles to wait before precharging an idle-bank.

SDRAM Trc Timing Value: This function specifies the minimum time between activate to activate of the
                                          same bank.

SDRAM Trp Timing Value: This function specifies the delay between a precharge command and an
                                           Activate command.

SDRAM Tras Timing Value: This function specifies the minimum SRAS[2.0] active time.

SDRAM Cas latency: This function specifies the delay from SRAS[2.0] to data valid.

Suite: The features (continued)